An ongoing trend in data processing systems is to replace a single mainframe-class processor with an array of linked microprocessors. The linked microprocessor architecture introduces a number of problems. One prevalent problem is to maintain system operation despite the failure of an individual microprocessor. This problem is especially acute if the failed microprocessor is the "master" microprocessor which coordinates the activities of the other microprocessors.
The traditional approach to resource reallocation after the failure of a microprocessor is to rely upon a static list which defines the new control scheme. For example, the static list might define that in the event that a first microprocessor goes down, then a forth microprocessor is to assume its tasks.
The problem with the static list approach relied upon in the prior art is that it is slow. The static list methodology requires that all of the system resources be established prior to making reallocation decisions. In other words, all of the system components must be polled or tested to determine which components are operative. Only after it is known which components are operative can the static list be invoked to establish a redistribution of resources. It would be highly desirable to reduce the amount of time required to make resource reallocation decisions after the failure of a microprocessor in a multiple microprocessor architecture.
Another problem with the static list reallocation approach is that it is resource intensive. That is, a resource redistribution scheme must be defined for each permutation of resource availability.
Another problem associated with prior art resource reallocation schemes is that they may result in the designation of more than one master microprocessor. This situation will "crash" the system, as the separate microprocessors produce conflicting system instructions.